Job Responsibility：
- Write Micro-Architecture and Integration Design Spec;
- Write RTL coding for core and bus standard trace logic, monitor signal map, debug control, etc.;
- Do IP level Linting / CDC check / synthesis / timing analysis / formality check;
- Assist on Verification Engineer to complete module to top level verification and debugging;
- Debug RTL and Gate Level waveform at top level to provide ECO solution in case of bug fixes;
- Take silicon debugging of the related module functionalities.
Job Qualification：
- MSEE or above with experience of digital design;
- Strong skills of Verilog RTL coding, simulation debug and ECO changes with netlist database;
- Hands on experience in EDA tools such as VCS, Spyglass, DC, PT, Equivalence check, etc.;
- Basic skills of script and be familiar with Shell, Perl, Python, etc.;
- Self-motivated, good team work spirit and communication skills;
- Following working experiences will be one advantage:
Experience in DDR/ CPU/ GPU design;
Experience in AXI/AHB/APB protocols and ARM-based fabric design;
Experience in core or bus trace and debug, signal monitoring, PCIe, JTAG related.
Job Responsibility：
Montage Technology has opened a new U.S. location in the Johns Creek, GA area offering a hybrid work environment. We are a leading semiconductor company specializing in datacenter, enterprise infrastructure and memory interface products. There will be many hands-on learning experiences with significant program ownership and career growth.
Founded in 2004, Montage Technology is a leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets. Montage Technology provides industry leading DDR2 to DDR5 memory interface products for the demanding cloud computing and data center markets. Our robust product portfolio includes the critical components required by the memory modules, such as a Registering Clock Driver (RCD), Data Buffer (DB), SPD EEPROM with Hub (SPD Hub), Temperature Sensor (TS) and Power Management IC (PMIC). Compliant with JEDEC specifications, these products are designed for a variety of memory modules such as RDIMM, LRDIMM, NVDIMM, UDIMM, SODIMM, MRDIMM, etc., to enable high-speed, large-capacity, high-reliability and low-power memory solutions for high-performance computing.
- Team environment with individual contributions to the design tasks;
- Full custom analog design of various blocks such as PLLs, oscillators, bandgap, LDO, voltage regulators and High voltage detection circuits;
- Provide feasibility study for size/performance/schedule;
- Plan and coordinate with Verification/AMS design to ensure full validation coverage;
- Provide floor-planning and support integration of digital & analog circuit at top chip level;
- Work in cooperation with the methodology and CAD groups;
- Interface between different teams to ensure successful path to production;
- Coordinate with other stakeholders in identifying needs and improvements.
Job Qualification：
- Experience in analog and low power design using advanced deep micron process;
- Proficient with Verilog RTL coding skills (Synchronous and Asynchronous state machines);
- Proficient with Hspice and other analog simulators;
- Experience with Cadence schematic capture;
- Experience with Linux;
- Good communication skills, ability to take ownership.
Job Responsibility：
- Design, evaluate and verify CMOS analog circuits ( PLL、DDR、USB、HDMI、ADAC、VDAC);
- Oversee layout and verification activities which include floor plan, LVS and DRC.
Job Qualification：
- Bachelor degree or Master degree in ASIC Design Relevant;
- Experience in RF/Analog IC design;
- Good fundamental in analysis and design of analog / mixed-signal circuits;
- Experience in Verilog, AHDL and/or Matlab;
- Ability to do layout and provide verification/debugging guidance;
- Solid knowledge of EDA design tools (Analog artist, spectre, HSPICE and nc-verilog ...);
- Familiar with Computer languages such as C, C++, perl;
- Experience in any of the following areas is preferred: PLL, high-speed I/O’s;
- Good communication skills and Good oral/written English.
Job Responsibility：
Montage Technology has opened a new U.S. location in the Johns Creek, GA area offering a hybrid work environment. We are a leading semiconductor company specializing in datacenter, enterprise infrastructure and memory interface products. There will be many hands-on learning experiences with significant program ownership and career growth.
Founded in 2004, Montage Technology is a leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets. Montage Technology provides industry leading DDR2 to DDR5 memory interface products for the demanding cloud computing and data center markets. Our robust product portfolio includes the critical components required by the memory modules, such as a Registering Clock Driver (RCD), Data Buffer (DB), SPD EEPROM with Hub (SPD Hub), Temperature Sensor (TS) and Power Management IC (PMIC). Compliant with JEDEC specifications, these products are designed for a variety of memory modules such as RDIMM, LRDIMM, NVDIMM, UDIMM, SODIMM, MRDIMM, etc., to enable high-speed, large-capacity, high-reliability and low-power memory solutions for high-performance computing.
- Validation: Develop and execute validation plans and test cases for DDR4 and DDR5 memory systems, ensuring compliance with industry standards. Validate memory component functionality, compatibility, and performance;
- Interconnect: Evaluate memory system equalization techniques and transmission line characteristics to optimize signal integrity and data transfer rates;
- Firmware and BIOS Development: Create firmware solutions to enhance memory system capabilities and compatibility;
- Margining Algorithms: Develop and implement margining algorithms to ensure robust operation under various operating conditions;
- Scripting and Programming: Utilize Python and C++ for test automation, firmware development, and data analysis to streamline validation processes;
- Test Development: Collaborate with design and architecture teams to design and execute innovative tests that stress memory systems to their limits;
- Data Analysis: Analyze validation results to identify and report issues, anomalies, and potential improvements in memory system performance;
- Cross-functional Collaboration: Collaborate with hardware and software teams to address and resolve validation and performance issues, ensuring product readiness for market release.
Job Qualification：
- Bachelor's or Master’s degree in electrical engineering or computer engineering;
- Strong experience in DDR4 and DDR5 memory system validation;
- 5+ years of relevant work experience;
- Experience with signal integrity and equalization techniques;
- Knowledge of DDR Training algorithms;
- Proficiency in Python and C++ programming for test automation, firmware development, and data analysis;
- Experience with memory controllers, firmware, and BIOS development is a strong plus;
- Solid understanding of memory system architecture and industry standards;
- Strong problem-solving skills and attention to detail;
- Excellent communication and teamwork skills;
- Experience in testing and validation methodologies;
- Experience mentoring junior engineers.
Job Responsibility：
- Participate ASIC digital verification for various IP/SoC projects;
- Create verification plans with designers;
- Develop DV architecture and verification environment;
- Verification execution and sign-off.
Job Qualification：
- Excellent team working style;
- Solid IP/SoC verification background;
- Mass production for verified IP/SoC;
- Bachelor with experiences on ASIC digital verification;
- Production experiences on verification strategies and testplans;
- Familiar with SystemVerilog/UVM for testbench creation, debug, reuse, constrained-random stimulus and functional coverage;
- Production experiences on ARM buses, such as AXI/AMBA/APB is a plus;
- Familiar with verification tools;
- Familiar with Linux, csh/Python or any script languages;
- Good English skills (read and write).
Job Responsibility：
Montage Technology has opened a new U.S. location in the Johns Creek, GA area offering a hybrid work environment. We are a leading semiconductor company specializing in datacenter, enterprise infrastructure and memory interface products. There will be many hands-on learning experiences with significant program ownership and career growth.
Founded in 2004, Montage Technology is a leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets. Montage Technology provides industry leading DDR2 to DDR5 memory interface products for the demanding cloud computing and data center markets. Our robust product portfolio includes the critical components required by the memory modules, such as a Registering Clock Driver (RCD), Data Buffer (DB), SPD EEPROM with Hub (SPD Hub), Temperature Sensor (TS) and Power Management IC (PMIC). Compliant with JEDEC specifications, these products are designed for a variety of memory modules such as RDIMM, LRDIMM, NVDIMM, UDIMM, SODIMM, MRDIMM, etc., to enable high-speed, large-capacity, high-reliability and low-power memory solutions for high-performance computing.
We are looking for a Principal level Digital Design Engineer with over 15 years of experience who will help architect and develop RTL for various products with the area of focus being DDR server-class memory controllers. The ideal candidate will have RTL to GDSII flow experience using industry standard tools. In addition, knowledge of embedded micro-controllers such as RISCV and I2C/I3C protocols are advantageous. Your contribution would be to work with other global team members in designing both building blocks for the various products, as well as designing the entire new product for the company.
- Mentor and lead cross functional teams to architect, develop and debug digital and mixed signal circuits;
- Design various logic & state machines in SystemVerilog/Verilog RTL;
- Develop and debug RTL, using industry-standard simulation and synthesis tools, along with LEC, CDC, Lint, DFT and STA tools;
- Provide PPA (Power, Performance, Area) and schedule estimates, as well as design specifications for the RTL;
- Coordinate with Verification/AMS design teams to ensure proper operation and functional and code coverage;
- Provide floor-planning and support integration of digital & analog circuits at top level;
- Work in cooperation with the methodology and CAD teams;
- Coordinate with other stakeholders in identifying needs and improvements.
Job Qualification：
- Must have 15 years of industry experience;
- Must have experience and deep understanding in the architecture definition of DDR4/5 server-class memory controllers;
- Understand how to obtain minimum latency and maximum bandwidth;
- Understand the tradeoff with command placement and scheduling, can efficiently manage activate and pre-charge commands;
- Familiar with ECC (SECDEC) and CRC;
- Knowledge of CHI/AXI interconnect and bus protocols;
- Knowledge of JEDEC memory standards;
- Experience in high speed and low power digital design in advanced deep sub-micron processes;
- Proficient with SystemVerilog/Verilog RTL, for both behavioral simulations and synthesis;
- Proficient with Design Compiler and PrimeTime;
- Programming/scripting know-how, e.g. Perl, Tcl and/or Python;
- Experience with Linux;
- Good communication skills, ability to take ownership;
- Experience with embedded micro-controllers is beneficial.
Job Responsibility：
- Firmware, driver, Middleware library, complier or security algorithm development;
- Unit test development and maintain;
- Document maintain;
- Troubleshoot, debug and maintain existing software;
- Performance tuning
Job Qualification：
- Bachelor or above degree in computer science or related technical field;
- Strong C/C++ programming ability;
- Familiar with Code development Toolchain under Linux;
- Self-motivated, good teamwork spirit and good communication skills;
- Preferred Qualifications:
Familiar with x86 or RISC-V architecture is preferred;
Familiar with Linux driver development is preferred;
Script language such as Python is a plus;
Linux kernel knowledge is a plus.
Job Responsibility：
Montage Technology has opened a new U.S. location in the Johns Creek, GA area. We are a leading semiconductor company specializing in datacenter, enterprise infrastructure and memory interface products. There will be many hands-on learning experiences with significant program ownership and career growth.
Founded in 2004, Montage Technology is a leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets. Montage Technology provides industry leading DDR2 to DDR5 memory interface products for the demanding cloud computing and data center markets. Our robust product portfolio includes the critical components required by the memory modules, such as a Registering Clock Driver (RCD), Data Buffer (DB), SPD EEPROM with Hub (SPD Hub), Temperature Sensor (TS) and Power Management IC (PMIC). Compliant with JEDEC specifications, these products are designed for a variety of memory modules such as RDIMM, LRDIMM, NVDIMM, UDIMM, SODIMM, MRDIMM, etc., to enable high-speed, large-capacity, high-reliability and low-power memory solutions for high-performance computing. In addition to our memory products, our portfolio also includes PCIe re-timers and CXL memory expanders.
- Validation: develop and execute validation plans and test cases for PCIe and CXL system interfaces, ensuring compliance with industry standards. Validate PCIe and CXL functionality, compatibility, and performance;
- Interconnect: evaluate interface equalization techniques and transmission line characteristics to optimize signal integrity and data transfer rates;
- Scripting and programming: utilize Python and C++ for test automation and data analysis to streamline validation processes;
- Test development: collaborate with design and architecture teams to design and execute innovative tests that stress the PCIe and CXL interfaces to their limits;
- Data analysis: analyze validation results to identify and report issues, anomalies, and potential improvements in performance;
- Cross-functional collaboration: collaborate with hardware and software teams to address and resolve validation and performance issues, ensuring product readiness for market release.
Job Qualification：
- Bachelor's or Master’s degree in electrical engineering or computer engineering;
- Strong experience in PCIe and CXL interface validation and debug;
- 5+ years of relevant work experience;
- Experience with signal integrity and equalization techniques;
- Knowledge of PCIe/CXL training and protocol flows;
- Proficiency in Python and C++ programming for test automation and data analysis.
- Experience with firmware and BIOS development is a plus;
- Solid understanding of server platform architecture and industry standards;
- Strong problem-solving skills and attention to detail;
- Excellent communication and teamwork skills;
- Experience in testing and validation methodologies;
- Experience mentoring junior engineers.
Job Responsibility：
- Perform RTL to GDSII design flow, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, EM/IR;
- Perform Full chip DRC/LVS/ANT/DFM;
- Participate in next generation physical design, methodology and flow development.
Job Qualification：
- Bachelor degree or Master degree in Microelectronics;
- Be familiar with RTL to GDSII design flow;
- Be familiar with EDA tool;
- Successful track records of taping out complex, 65/40/28 nm SOC chips;
- Be familiar with Computer languages such as C, C++, perl/TCL/C-shell;
- Be familiar with DC、PT、FM、DFT;
- Self-motivated and good communication skills.
About Us:
Montage Technologies has opened a new U.S. location in the Johns Creek, GA area. We are a leading semiconductor company specializing in enterprise class memory products. There will be many hands-on learning experiences with significant program ownership and career growth.
Founded in 2004, Montage Technology is a leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets. Montage Technology provides industry leading DDR2 to DDR5 memory interface products for the demanding cloud computing and data center markets. Our robust product portfolio includes the critical components required by the memory modules, such as Registering Clock Driver (RCD), Data Buffer (DB), SPD EEPROM with Hub (SPD Hub), Temperature Sensor (TS) and Power Management IC (PMIC). Compliant with JEDEC specifications, these products are designed for a variety of memory modules such as RDIMM, LRDIMM, NVDIMM, UDIMM, SODIMM, MRDIMM, etc., to enable high-speed, large-capacity, high-reliability and low-power memory solutions for high-performance computing.
Job Description:
As a Validation/Hardware Engineer, you will be responsible for engineering characterization, and failure analysis of DDR memory, CXL, PCIe, and PMIC systems at Montage Technology, you will be a key contributor in ensuring the reliability, performance, and compatibility of our enterprise-class components and technologies. You will work closely with cross-functional teams to develop and execute validation plans, build validation hardware, and implement automation to ensure our system solutions meet the highest quality standards. Key Responsivities are:
- Developing tools and methods for programming, training and validating DDR, CXL, PCIe, and PMIC hardware;
- Conducing engineering characterization, customer support, and failure analysis of DDR, CXL, PCIe, and PMIC hardware to understand its performance characteristics, designing and running experiments, analyzing data, and presenting the findings to other team members;
- Performing testing and validating early silicon against industry specifications, analyzing the performance and behavior of security, DDR, CXL, PCIe, and PMIC hardware to ensure that they meet the required specifications;
- Investigating and resolving issues identified during testing to identify the root cause of failures and work closely with design and development teams to find solutions;
- Evaluating the performance of DDR, CXL, PCIe, and PMIC hardware by measuring data transfer rates, latency, power consumption, and other relevant parameters, and analyzing performance data and identify areas for improvement;
- Conducting failure analysis of system hardware to understand the roots of bugs and methods of preventions in the future system debugging, margin or training failures;
- Maintaining detailed test plans, test reports, and documentation of validation procedures, and documenting any issues encountered, along with the steps taken to reproduce and resolve them;
- Cross-functional collaboration: collaborate with hardware and software teams to address and resolve validation and performance issues, ensuring product readiness for market release.
Qualifications:
- Bachelor's or Master’s degree in Electrical Engineering;
- Strong experience in DDR4 and DDR5 memory system, PCIe, or PMIC validation;
- 3+ years of relevant work experience;
- Experience with signal integrity and equalization techniques;
- Proficiency in Python and C++ programming for test automation, firmware development, and data analysis;
- Experience with memory controllers, firmware, and BIOS development is a strong plus;
- Solid understanding of memory system architecture and industry standards;
- Strong problem-solving skills and attention to detail;
- Excellent communication and teamwork skills;
- Experience in testing and validation methodologies.